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DS2502 1 kbit addonly memory DS2502 062598 1/21 features ? 1024 bits electrically programmable read only memory (eprom) communicates with the economy of one signal plus ground ? unique, factorylasered and tested 64bit registra- tion number (8bit family code + 48bit serial number + 8bit crc tester) assures absolute traceability because no two parts are alike ? builtin multidrop controller ensures compatibility with other microlan tm products ? eprom partitioned into four 256bit pages for ran- domly accessing packetized data records ? each memory page can be permanently writepro- tected to prevent tampering ? device is an aadd onlyo memory where additional data can be programmed into eprom without disturbing existing data ? architecture allows software to patch data by super- seding an old page in favor of a newly programmed page ? reduces control, address, data, power, and program- ming signals to a single data pin ? directly connects to a single port pin of a microproces- sor and communicates at up to 16.3k bits per second ? 8bit family code specifies DS2502 communications requirements to reader ? presence detector acknowledges when the reader first applies voltage ? low cost to92 or 8pin soic and tsoc surface mount package ? reads over a wide voltage range of 2.8v to 6.0v from 40 c to +85 c; programs at 11.5v to 12.0v from 40 c to +50 c pin assignment gnd data nc bottom view to92 3 2 1 dallas DS2502 gnd nc data nc nc nc nc nc 1 2 3 4 8 7 6 5 8pin soic (150 mil) tsoc package nc nc nc gnd data nc 1 2 3 6 5 4 top view 3.7 x 4.0 x 1.5 mm see mech. drawings section ordering information DS2502 to92 package DS2502s 8pin soic package DS2502p 6pin tsoc package DS2502t tape & reel version of DS2502 DS2502y tape & reel version of DS2502s DS2502v tape & reel version of DS2502p silicon label description the DS2502 1 kbit addonly memory identifies and stores relevant information about the product to which it is associated. this lot or productspecific information can be accessed with minimal interfacefor example, a single port pin of a microcontroller. the DS2502 con- sists of a factorylasered registration number that includes a unique 48bit serial number, an 8bit crc, and an 8bit family code (09h) plus 1kbit of eprom which is userprogrammable. the power to program and read the DS2502 is derived entirely from the 1wire tm communication line.
DS2502 062598 2/21 data is transferred serially via the 1wire protocol which requires only a single data lead and a ground return. the entire device can be programmed and then writeprotected if desired. alternatively, the part may be programmed multiple times with new data being appended to, but not overwriting, existing data with each subsequent programming of the device. note: individual bits can be changed only from a logical 1 to a logical 0, never from a logical 0 to a logical 1. a provision is also included for indicating that a certain page or pages of data are no longer valid and have been replaced with new or updated data that is now residing at an alternate page address. this page address redirection allows software to patch data and enhance the flexibility of the device as a standalone database. the 48bit serial number that is factorylasered into each DS2502 provides a guaranteed unique identity which allows for absolute traceability. the familiar to92 or soic or tsoc packages provide a compact enclosure that allows standard assembly equipment to handle the device easily for attachment to printed circuit boards or wiring. typical applications include storage of calibration constants, maintenance records, asset tracking, product revision status, and access codes. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the DS2502. the DS2502 has three main data compo- nents: 1) 64bit lasered rom, 2) 1024bit eprom, and 3) eprom status bytes. the device derives its power for read operations entirely from the 1wire com- munication line by storing energy on an internal capaci- tor during periods of time when the signal line is high and continues to operate off of this aparasiteo power source during the low times of the 1wire line until it returns high to replenish the parasite (capacitor) supply. during programming, 1wire communication occurs at normal voltage levels and then is pulsed momentarily to the pro- gramming voltage to cause the selected eprom bits to be programmed. the 1wire line must be able to pro- vide 12 volts and 10 milliamperes to adequately pro- gram the eprom portions of the part. whenever pro- gramming voltages are present on the 1wire line a special high voltage detect circuit within the DS2502 generates an internal logic signal to indicate this condi- tion. the hierarchical structure of the 1wire protocol is shown in figure 2. the bus master must first provide one of the six rom function commands, 1) read rom, 2) match rom, 3) search rom, 4) skip rom. these commands operate on the 64bit lasered rom portion of each device and can singulate a specific device if many are present on the 1wire line as well as indicate to the bus master how many and what types of devices are present. the protocol required for these rom function commands is described in figure 9. after a rom function command is successfully executed, the memory functions that operate on the eprom portions of the DS2502 become accessible and the bus master may issue any one of the five memory function commands specific to the DS2502 to read or program the various data fields. the protocol for these memory function commands is described in fig- ure 5. all data is read and written least significan bit first. 64bit lasered rom each DS2502 contains a unique rom code that is 64 bits long. the first eight bits are a 1wire family code. the next 48 bits are a unique serial number. the last eight bits are a crc of the first 56 bits. (see figure 3). the 64bit rom and rom function control section allow the DS2502 to operate as a 1wire device and fol- low the 1wire protocol detailed in the section a1wire bus system.o the memory functions required to read and program the eprom sections of the DS2502 are not accessible until the rom function protocol has been satisfied. this protocol is described in the rom func- tions flow chart (figure 9). the 1wire bus master must first provide one of four rom function commands: 1) read rom, 2) match rom, 3) search rom, or 4) skip rom. after a rom function sequence has been suc- cessfully executed, the bus master may then provide any one of the memory function commands specific to the DS2502 (figure 6). the 1wire crc of the lasered rom is generated using the polynomial x 8 + x 5 + x 4 + 1. figure 4 shows a hard- ware implementation of this crc generator. additional information about the dallas semiconductor 1wire cyclic redundancy check is available in the book of ds19xx i button standards. the shift register acting as the crc accumulator is initialized to zero. then starting with the least significant bit of the family code, one bit at a time is shifted in. after the eighth bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the eight bits of crc should return the shift register to all zeroes.
DS2502 062598 3/21 DS2502 block diagram figure 1 parasite power 1wire function control 64bit lasered rom program voltage detect memory function control 8bit scratchpad 8bit crc generator 1024bit eprom (4 pages of 32 bytes) eprom status bytes data 1wire bus
DS2502 062598 4/21 hierarchical structure for 1wire protocol figure 2 1wire rom function commands (see figure 9) DS2502specific memory function commands (see figure 6) command level: available commands: data field affected: read rom match rom search rom skip rom 64bit rom 64bit rom 64bit rom n/a write memory 1024bit eprom write status byte read memory read status byte read data/generate eprom status bytes 1024bit eprom eprom status bytes 1024bit eprom bus master 1wire bus other devices DS2502 8bit crc 64bit lasered rom figure 3 8bit crc code 48bit serial number 8bit family code (09h) msb lsb msb lsb msb lsb 1wire crc generator figure 4 (msb) xor xor xor input (lsb)
DS2502 062598 5/21 1024bits eprom the memory map in figure 5 shows the 1024bit eprom section of the DS2502 which is configured as four pages of 32 bytes each. the 8bit scratchpad is an additional register that acts as a buffer when program- ming the memory. data is first written to the scratchpad and then verified by reading an 8bit crc from the DS2502 that confirms proper receipt of the data. if the buffer contents are correct, a programming voltage should be applied and the byte of data will be written into the selected address in memory. this process insures data integrity when programming the memory. the details for reading and programming the 1024bit eprom portion of the DS2502 are given in the memory function commands section. eprom status bytes in addition to the 1024 bits of data memory the DS2502 provides 64 bits of status memory accessible with sep- arate commands. the eprom status bytes can be read or programmed to indicate various conditions to the software interrogat- ing the DS2502. the first byte of the eprom status memory contain the write protect page bits which inhibit programming of the corresponding page in the 1024bit main memory area if the appropriate write protection bit is programmed. once a bit has been pro- grammed in the write protect page byte, the entire 32 byte page that corresponds to that bit can no longer be altered but may still be read. the next four bytes of the eprom status memory con- tain the page address redirection bytes which indicate if one or more of the pages of data in the 1026bit eprom section have been invalidated and redirected to the page address contained in the appropriate redirection byte. the hardware of the DS2502 makes no decisions based on the contents of the page address redirection bytes. these additional bytes of status eprom technology, bits within a page can be changed from a logical 1 to a logical 0 by programming, but can- not be changed back. therefore, it is not possible to sim- ply rewrite a page if the data requires changing or updat- ing, but with space permitting, an entire page of data can be redirected to another page within the DS2502 by writ- ing the one's complement of the new page address into the page address redirection byte that corresponds to the original (replaced) page. this architecture allows the user's software to make a adata patcho to the eprom by indicating that a particu- lar page or pages should be replaced with those indi- cated in the page address redirection bytes. if a page address redirection byte has a ffh value, the data in the main memory that corresponds to that page is valid. if a page address redirection byte has some other hex value, the data in the page corresponding to that redirection byte is invalid, and the valid data can now be found at the one's complement of the page address indicated by the hex value stored in the associated page address redirection byte. a value of fdh in the redirection byte for page 1, for example, would indicate that the updated data is now in page 2. the details for reading and programming the eprom status memories portion of the DS2502 are given in the memory function commands section. memory function commands the amemory function flow charto (figure 6) describes the protocols necessary for accessing the various data fields within the DS2502. the memory function control section, 8bit scratchpad, and the program voltage detect circuit combine to interpret the commands issued by the bus master and create the correct control signals within the device. a threebyte protocol is issued by the bus master. it is comprised of a command byte to determine the type of operation and two address bytes to determine the specific starting byte location within a data field. the command byte indicates if the device is to be read or written. writing data involves not only issuing the correct command sequence by also providing a 12 volt programming voltage at the appropri- ate times. to execute a write sequence, a byte of data is first loaded into the scratchpad and then programmed into the selected address. write sequences always occur a byte at a time. to execute a read sequence, the starting address is issued by the bus master and data is read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequence is issued. all bits transferred to the DS2502 and received back by the bus master are sent least significant bit first.
DS2502 062598 6/21 DS2502 memory map figure 5 0000h 1024bit eprom 8bit scratchpad page 0 32 bytes page 1 32 bytes page 2 32 bytes page 3 32 bytes 0020h 0040h 0060h starting address eprom status bytes 7 bit 0 bit 1 bit 2 bit 3 bit 47 factory programmed 00h write protect page 0 write protect page 1 write protect page 2 write protect page 3 bitmap of used pages (reserved for tmex) reserved for future expans ion page address redirection byte for page 3 page address redirection byte for page 2 page address redirection byte for page 3 page address redirection byte for page 0 6 54 32 10 address: 0007h (msb) 0006h 0005h 0004h 0003h 0002h 0001h 0000h (lsb)
DS2502 062598 7/21 memory function flow chart figure 6 f0h read memory ? n bus master t x ta1 (t7:t0) bus master t x ta2 (t15:t8) bus master r x 8bit crc of command and address y bus master r x data from data memory bus master t x reset ? end of data memory ? DS2502 increments address counter aah read status ? bus master t x ta1 (t7:t0) bus master t x ta2 (t15:t8) bus master rx 8bit crc of command and address bus master r x data from status memory bus master t x reset ? end of page ? bus master r x 8bit crc of data bus master t x reset ? bus master r x 1's DS2502 increments address counter y n y n y n y y n n y n bus master t x reset ? n bus master t x reset ? bus master r x 1's y n bus master t x reset ? y y master t x memory function command crc correct ? n crc correct ? n y DS2502 t x presence pulse bus master r x 8bit crc of status data n n master t x reset y
DS2502 062598 8/21 memory function flow chart (cont'd) figure 6 bus master t x reset c3h read data & generate 8bit crc ? n bus master t x ta1 (t7:t0) bus master t x ta2 (t15:t8) bus master r x 8bit crc of command and address y crc correct ? DS2502 increments address counter n bus master r x data from data memory bus master t x reset ? end of page ? bus master r x 8bit crc of preceding page of data end of memory ? bus master t x reset ? bus master r x 1's y n n y n y y n to write commands legend: decision made by the master decision made by ds2506 bus master t x reset crc correct ? n y DS2502 tx presence pulse
DS2502 062598 9/21 memory function flow chart (cont'd) figure 6 0fh write memory ? n bus master t x ta1 (t7:t0) bus master t x ta2 (t15:t8) bus master r x 8bit crc of command, address, data (1 st pass) crc of address, data (subsequent passes) crc correct ? y bus master t x data byte (d7:d0) bus master t x program pulse bus master r x byte from eprom end of data memory ? DS2502 increments address counter DS2502 loads lsb of new address into crc generator master t x reset 55h write status ? bus master t x ta1 (t7:t0) bus master t x ta2 (t15:t8) crc correct ? bus master t x data byte (d7:d0) bus master t x program pulse bus master r x byte from eprom master t x reset n y y n n y n y y eprom byte= data byte ? end of status memory ? DS2502 increments address counter DS2502 loads lsb of new address into crc generator y n y eprom byte= correct ? bus master r x crc16 of command, address, data (1 st pass) crc16 of address, data (subsequent passes) n n bus master t x reset DS2502 copies scratchpad to status eprom DS2502 copies scratchpad to data eprom from read commands DS2502 t x presence pulse
DS2502 062598 10/21 read memory [f0h] the read memory command is used to read data from the 1024bit eprom data field. the bus master follows the command byte with a twobyte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. an 8bit crc of the command byte and address bytes is computed by the DS2502 and read back by the bus master to confirm that the correct command word and starting address were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus mas- ter is correct, the bus master issues read time slots and receives data from the DS2502 starting at the initial address and continuing until the end of the 1024bit data field is reached or until a reset pulse is issued. if reading occurs through the end of memory space, the bus master may issue eight additional read time slots and the DS2502 will respond with a 8bit crc of all data bytes read from the initial starting byte through the last byte of memory. after the crc is received by the bus master, any subsequent read time slots will appear as logical 1s until a reset pulse is issued. any reads ended by a reset pulse prior to reaching the end of memory will not have the 8bit crc available. typically a 16bit crc would be stored with each page of data to insure rapid, errorfree data transfers that eliminate having to read a page multiple times to deter- mine if the received data is correct or not. (see book of ds19xx i button standards, chapter 7 for the recom- mended file structure to be used with the 1wire envi- ronment). if crc values are imbedded within the data, a reset pulse may be issued at the end of memory space during a read memory command. read status [aah] the read status command is used to read data from the eprom status data field. the bus master follows the command byte with a twobyte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. an 8bit crc of the command byte and address bytes is computed by the DS2502 and read back by the bus master to confirm that the correct command word and starting address were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus mas- ter is correct, the bus master issues read time slots and receives data from the DS2502 starting at the supplied address and continuing until the end of the eprom sta- tus data field is reached. at that point the bus master will receive an 8bit crc that is the result of shifting into the crc generator all of the data bytes from the initial start- ing byte through the final factoryprogrammed byte that contains the 00h value. this feature is provided since the eprom status information may change over time making it impossible to program the data once and include an accompanying crc that will always be valid. therefore, the read sta- tus command supplies a 8bit crc that is based on and always is consistent with the current data stored in the eprom status data field. after the 8bit crc is read, the bus master will receive logical 1s from the DS2502 until a reset pulse is issued. the read status command sequence can be ended at any point by issuing a reset pulse. read data/generate 8bit crc [c3h] the read data/generate 8bit crc command is used to read data from the 1024bit eprom data field. the bus master follows the command byte with a twobyte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. an 8bit crc of the command byte and address bytes is computed by the DS2502 and read back by the bus master to confirm that the correct command word and starting address were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, the bus master issues read time slots and receives data from the DS2502 starting at the initial address and continuing until the end of a 32byte page is reached. at that point the bus master will send eight additional read time slots and receive an 8bit crc that is the result of shifting into the crc generator all of the data bytes from the initial starting byte to the last byte of the current page. once the 8bit crc has been received, data is again read from the 1024bit eprom data field starting at the next page. this sequence will continue until the final page and its accompanying crc are read by the bus master. thus each page of data can be considered to be 33 bytes long, the 32 bytes of userprogrammed eprom data and an 8bit crc that gets generated automatically at the end of each page. this type of read differs from the read memory com- mand which simple reads each page until the end of address space is reached. the read memory com-
DS2502 062598 11/21 mand only generates an 8bit crc at the end of memory space that often might be ignored, since in many applications the user would store a 16bit crc with the data itself in each page of the 1024bit eprom data field at the time the page was programmed. the read data/generate 8bit crc command pro- vides and alternate read capability for applications that are abitorientedo rather than apage orientedo where the 1024but eprom information may change over time within a page boundary making it impossible to program the page once and include an accompanying crc that will always be valid. therefore, the read data/gener- ate 8bit crc command concludes each page with the DS2502 generating and supplying an 8bit crc that is based on and therefore is always consistent with the current data stored in each page of the 1024bit eprom data field. after the 8bit crc of the last page is read, the bus master will receive logical 1s from the DS2502 until a reset pulse is issued. the read data/ generate 8bit crc command sequence can be exited at any point by issuing a reset pulse. write memory [0fh] the write memory command is used to program the 1024bit eprom data field. the bus master will follow the command byte with a twobyte starting address (ta1=(t7:t0), ta2=(t5:t8)) and a byte of data (d7:d0). an 8bit crc of the command byte, address bytes, and data byte is computed by the DS2502 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. the highest starting address within the DS2502 is 007fh. if the bus master sends a starting address higher than this, the nine most significant address bits are set to zero by the internal circuitry of the chip. this will result in a mismatch between the crc calculated by the DS2502 and the crc calculated by the bus master, indicating an error condition. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is cor- rect, a programming pulse (12 volts on the 1wire bus for 480 m s) is issued by the bus master. prior to pro- gramming, the entire unprogrammed 1024bit eprom data field will appear as logical 1s. for each bit in the data byte provided by the bus master that is set to a log- ical 0, the corresponding bit in the selected byte of the 1024bit eprom will be programmed to a logical 0 after the programming pulse has been applied at that byte location. after the 480 m s programming pulse is applied and the data line returns to a 5 volt level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. the DS2502 responds with the data from the selected eprom address sent least significant bit first. this byte contains the logical and of all bytes written to this eprom data address. if the eprom data byte contains 1s in bit positions where the byte issued by the master contains 0s, a reset pulse should be issued and the current byte address should be programmed again. if the DS2502 eprom data byte contains 0s in the same bit positions as the data byte, the programming was successful and the DS2502 will automatically increment its address counter to select the next byte in the 10 24bit eprom data field. the least significant byte of the new twobyte address will also be loaded into the 8bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the DS2502 receives this byte of data into the scratchpad, it also shifts the data into the crc genera- tor that has been preloaded with the lsb of the current address and the result is an 8bit crc of the new data byte and the lsb of the new address. after suppling the data byte, the bus master will read this 8bit crc from the DS2502 with eight read time slots to confirm that the address incremented properly and the data byte was received correctly. if the crc is incorrect, a reset pulse must be issued and the write memory command sequence must be restarted. if the crc is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through the write memory flow chart will generate an 8bit crc value that is the result of shifting the command byte into the crc generator, followed by the two address bytes, and finally the data byte. subsequent passes through the write memory flow chart due to the DS2502 automatically increment- ing its address counter will generate an 8bit crc that is the result of loading (not shifting) the lsb of the new (incremented) address into the crc generator and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the DS2502) is made entirely by the bus master, since the DS2502 will not be able to determine if the 8bit crc calculated by the bus master agrees with the 8bit crc calculated by the DS2502. if
DS2502 062598 12/21 an incorrect crc is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the DS2502. also note that the DS2502 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected eprom byte. the deci- sion to continue is again made entirely by the bus mas- ter, therefore if the eprom data byte does not match the supplied data byte does not match the supplied data byte but the master but the master continues with the write memory command, incorrect programming could occur within the DS2502. the write memory command sequence can be exited at any point by issuing a reset pulse. write status [55h] the write status command is used to program the eprom status data field. the bus master will follow the command byte with a twobyte starting address (ta1=(t7:t0), ta2=(t15:t8)) and a byte of status data (d7:d0). an 8bit crc of the command byte, address bytes, and data byte is computed by the DS2502 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is cor- rect, a programming pulse (12 volts on the 1wire bus for 480 m s) is issued by the bus master. prior to pro- gramming, the first seven bytes of the eprom status data field will appear as logical 1s. for each bit in the data byte provided by the bus master that is set to a log- ical 0, the corresponding bit in the selected byte of the eprom status data field will be programmed to a log- ical 0 after the programming pulse has been applied at the byte location. the eighth byte of the eprom status byte data field is factoryprogrammed to contain 00h. after the 480 m s programming pulse is applied and the data line returns to a 5 volt level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. the DS2502 responds with the data from the selected eprom status address sent least significant bit first. this byte contains the logical and of all bytes written to this eprom status byte address. if the eprom status byte contains 1s in bit positions where the byte issued by the master contained 0s, a reset pulse should be issued and the current byte address should be programmed again. if the DS2502 eprom status byte contains 0s in the same bit posi- tions as the data byte, the programming was successful and the DS2502 will automatically increment its address counter to select the next byte in the eprom status data field. the least significant byte of the new twobyte address will also be loaded into the 8bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the DS2502 receives this byte of data into the scratchpad, it also shifts the data into the crc genera- tor that has been preloaded with the lsb of the current address and the result is an 8bit crc of the new data byte and the lsb of the new address. after supplying the data byte, the bus master will read this 8bit crc from the DS2502 with eight read time slots to confirm that the address incremented properly and the data byte was received correctly. if the crc is incorrect, a reset pulse must be issued and the write status command sequence must be restarted. if the crc is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through the write status flow chart will generate an 8bit crc value that is the result of shifting the command byte into the crc generator, followed by the two address bytes, and finally the data byte. subsequent passes through the write status flow chart due to the DS2502 automatically incrementing its address counter will generate an 8bit crc that is the result of loading (not shifting) the lsb of the new (incremented) address into the crc generator and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the DS2502) is made entirely by the bus master, since the DS2502 will not be able to determine if the 8bit crc calculated by the bus master agrees with the 8bit crc calculated by the DS2502. if an incorrect crc is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the DS2502. also note that the DS2502 will always increment its internal address counter after the receipt of the eight read time slots used ot confirm the programming of the selected eprom byte. the deci- sion to continue is again made entirely by the bus mas- ter, therefore if the eprom data byte does not match the supplied data byte but the master continues with the write status command, incorrect programming could occur within the DS2502. the write status command sequence can be ended at any point by issuing a reset pulse.
DS2502 062598 13/21 1wire bus system the 1wire bus is a system which has a single bus mas- ter and one or more slaves. in all instances, the DS2502 is a slave device. the bus master is typically a micro- controller. the discussion of this bus system is broken down into three topics: hardware configuration, transac- tion sequence, and 1wire signalling (signal type and timing). a 1wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of ds19xx i button standards. hardware configuration the 1wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1wire bus must have an open drain connection or 3state outputs. the DS2502 is an open drain part with an internal circuit equivalent to that shown in figure 7. the bus master can be the same equivalent circuit. if a bidirectional pin is not available, separate output and input pins can be tied together. the bus master requires a pullup resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in figures 8a and 8b. the value of the pullup resistor should be approximately 5k w for short line lengths. a multidrop bus consists of a 1wire bus with multiple slaves attached. at regular speed the 1wire bus has a maximum data rate of 16.3k bits per second. if the bus master is also required to perform programming of the eprom portions of the DS2502, a programming supply capable of delivering up to 10 milliamps at 12 volts for 480 m s is required. the idle state for the 1wire bus is high. if, for any reason, a transaction needs to be sus- pended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16 m s (overdrive speed) or more than 120 m s (regular speed), one or more of the devices on the bus may be reset. transaction sequence the sequence for accessing the DS2502 via the 1wire port is as follows: ? initialization ? rom function command ? memory function command ? read/write memory/status initialization all transactions on the 1wire bus begin with an initial- ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the DS2502 is on the bus and is ready to operate. for more details, see the a1wire signallingo section. rom function commands once the bus master has detected a presence, it can issue one of the six rom function commands. all rom function commands are eight bits long. a list of these commands follows (refer to flowchart in figure 9): read rom [33h] this command allows the bus master to read the DS2502's 8bit family code, unique 48bit serial num- ber, and 8bit crc. this command can be used only if there is a single DS2502 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wiredand result). match rom [55h] the match rom command, followed by a 64bit rom sequence, allows the bus master to address a specific DS2502 on a multidrop bus. only the DS2502 that exactly matches the 64bit rom sequence will respond to the subsequent memory function command. all slaves that do not match the 64bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus.
DS2502 062598 14/21 DS2502 equivalent circuit figure 7 5 m a typ. . 100 w mosfet t x r x data ground bus master circuit figure 8 bus master v dd ttlequivalent port pins 5k w b) standard ttl v dd 5k w programming pulse 12v (10 ma min.) to data connection of DS2502 bus master v dd v dd ds5000 or 8051 equivalent open drain port pin r x t x a) open drain 12v to data connections of DS2502 5k w 10k w 10k w pgm d s d s s d d s 2n7000 2n7000 2n7000 470 pf vp0300l or vp0106n3 or bss110 r x t x capacitor added to reduce coupling on data line due to programming signal switching
DS2502 062598 15/21 rom functions flow chart figure 9 n y y y DS2502 t x presence pulse 33h read rom command 55h match rom command f0h search rom command cch skip rom command DS2502 t x family code 1 byte bit 0 match? bit 0 match? bit 1 match? bit 1 match? bit 63 match? bit 63 match? DS2502 t x serial number 6 bytes DS2502 t x crc byte n nn y y y nn y n n y y y DS2502 t x bit 0 DS2502 t x bit 0 DS2502 t x bit 1 DS2502 t x bit 1 DS2502 t x bit 63 DS2502 t x bit 63 master t x bit 1 master t x bit 0 master t x bit 0 master t x bit 1 master t x bit 63 master t x bit 63 master t x reset pulse master t x rom function command n n 1) master t x memory function command (see figure 6)
DS2502 062598 16/21 skip rom [cch] this command can save time in a single drop bus sys- tem by allowing the bus master to access the memory functions without providing the 64bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wiredand result). search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1wire bus or their 64bit rom codes. the search rom com- mand allows the bus master to use a process of elimina- tion to identify the 64bit rom codes of all slave devices on the bus. the rom search process is the repetition of a simple 3step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, 3step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be identified by additional passes. see chapter 5 of the book of ds19xx i button standards for a comprehensive discussion of a rom search, including an actual example. 1wire signaling the DS2502 requires strict protocols to insure data integrity. the protocol consists of five types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, read data and pro- gram pulse. all these signals except presence pulse are initiated by the bus master. the initialization sequence required to begin any communication with the DS2502 is shown in figure 10. a reset pulse followed by a pres- ence pulse indicates the DS2502 is ready to accept a rom command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 m s at regular speed, 48 m s at overdrive speed). the bus master then releases the line and goes into receive mode (rx). the 1wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the data pin, the DS2502 waits (t pdh , 1560 m s) and then transmits the presence pulse (t pdl , 60240 m s). read/write time slots the definitions of write and read time slots are illustrated in figure 11. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the DS2502 to the master by triggering a delay circuit in the DS2502. during write time slots, the delay circuit determines when the DS2502 will sample the data line. for a read data time slot, if a a0o is to be transmitted, the delay circuit determines how long the DS2502 will hold the data line low overriding the 1 gen- erated by the master. if the data bit is a a1o, the device will leave the read data time slot unchanged. program pulse to copy data from the 8bit scratchpad to the 1024bit eprom memory or status memory, a program pulse of 12 volts is applied to the data line after the bus master has confirmed that the crc for the current byte is cor- rect. during programming, the bus master controls the transition from a state where the data line is idling high via the pullup resistor to a state where the data line is actively driven to a programming voltage of 12 volts pro- viding a minimum of 10 ma of current to the DS2502. this programming voltage (figure 12) should be applied for 480 m s, after which the bus master returns the data line to an idle high state controlled by the pullup resistor. note that due to the high voltage pro- gramming requirements for any 1wire eprom device, it is not possible to multidrop noneprom based 1wire devices with the DS2502 during pro- gramming. an internal diode within the noneprom based 1wire devices will attempt to clamp the data line at approximately 8 volts and could potentially damage these devices. crc generation the DS2502 has an 8bit crc stored in the most signif- icant byte of the 64bit rom. the bus master can com- pute a crc value from the first 56 bits of the 64bit rom and compare it to the value stored within the DS2502 to determine if the rom data has been received errorfree by the bus master. the equivalent polynomial function of this crc is: x 8 + x 5 + x 4 +1. under certain conditions, the DS2502 also generates an 8bit crc value using the same polynomial function shown above and provides this value to the bus master to validate the transfer of command, address, and data bytes from the bus master to the DS2502. the memory function flow chart of figure 6 indicates that the DS2502 computes an 8bit crc for the command, address, and data bytes received for the write memory and the write status commands and then outputs this value to the bus master to confirm proper transfer. simi- larly the DS2502 computes an 8bit crc for the com- mand and address bytes received from the bus master
DS2502 062598 17/21 for the read memory, read status, and read data/ generate 8bit crc commands to confirm that these bytes have been received correctly. the crc genera- tor on the DS2502 is also used to provide verification of errorfree data transfer as each page of data from the 1024bit eprom is sent to the bus master during a read data/generate 8bit crc command, and for the eight bytes of information in the status memory field. in each case where a crc is used for data transfer val- idation, the bus master must calculate a crc value using the polynomial function given above and compare the calculated value to either the 8bit crc value stored in the 64bit rom portion of the DS2502 (for rom reads) or the 8bit crc value computed within the DS2502. the comparison of crc values and decision to continue with an operation are determined entirely by the bus master. there is no circuitry on the DS2502 that prevents a command sequence from proceeding if the crc stored in or calculated by the DS2502 does not match the value generated by the bus master. proper use of the crc as outlined in the flow chart of figure 6 can result in a communication channel with a very high level of integrity. for more details on generating crc values including example implementations in both hard- ware and software, see the book of ds19xx i button standards. initialization procedure areset and presence pulseso figure 10 t rsth t rstl t r v pullup v pullup min v ih min v il max 0v t pdh t pdl resistor master ds2506 master r x apresence pulseo master t x areset pulseo 480 m s < t rstl < * 480 m s < t rsth < (includes recovery time) 15 m s < t pdh < 60 m s 60 m s < t pdl < 240 m s * in order not to mask interrupt signalling by other devices on the 1wire bus, t rstl + t r should always be less than 960 m s.
DS2502 062598 18/21 read/write timing diagram figure 11 writeone time slot 60 m s t rec t low1 v pullup v pullup min v ih min v il max 0v 15 m s DS2502 sampling window t slot 60 m s < t slot < 120 m s 1 m s < t low1 < 15 m s 1 m s < t rec < writezero time slot v pullup v pullup min v ih min v il max 0v t slot t rec t low0 DS2502 sampling window 60 m s 15 m s 60 m s < t low0 < t slot < 120 m s 1 m s < t rec < readdata time slot v pullup v pullup min v ih min v il max 0v t slot t rec t rdv t lowr 60 m s < t slot < 120 m s 1 m s < t lowr < 15 m s 0 < t release < 45 m s 1 m s < t rec < t rdv = 15 m s t release master sampling window resistor master DS2502
DS2502 062598 19/21 program pulse timing diagram figure 12 >5 m s line type legend: v pullup gnd v pp >5 m s 480 m s normal 1wire communication ends normal 1wire communication resumes bus master active high (12v @ 10 ma) t rp t fp t dp t dv resistor pullup t pp
DS2502 062598 20/21 absolute maximum ratings* voltage on any pin relative to ground 0.5v to +12.0v operating temperature 40 c to +85 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operation sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (v pup =2.8v to 6.0v; 40 c to +85 c) parameter symbol min typ max units notes logic 1 v ih 2.2 v cc +0.3 v 1, 6 logic 0 v il 0.3 +0.8 v 1, 11 output logic low @ 4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1, 2 input load current i l 5 m a 3 operating charge q op 30 nc 7, 8 programming voltage @ 10 ma v pp 11.5 12.0 v capacitance (t a = 25 c) parameter symbol min typ max units notes data (1wire) c in/out 800 pf 9 ac electrical characteristics regular speed (v pup =2.8v to 6.0v; 40 c to +85 c) parameter symbol min typ max units notes time slot t slot 60 120 m s write 1 low time t low1 1 15 m s write 0 low time t low0 60 120 m s read data valid t rdv exactly 15 m s release time t release 0 15 45 m s read data setup t su 1 m s 5 recovery time t rec 1 m s reset time high t rsth 480 m s 4 reset time low t rstl 480 m s presence detect high t pdhigh 15 60 m s presence detect low t pdlow 60 240 m s delay to program t dp 5 m s 10 delay to verify t dv 5 m s 10 program pulse width t pp 480 5000 m s 10, 12 program voltage rise time t rp 0.5 5.0 m s 10 program voltage fall time t fp 0.5 5.0 m s 10
DS2502 062598 21/21 notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage. 3. input load is to ground. 4. an additional reset or communication sequence cannot begin until the reset high time has expired. 5. read data setup time refers to the time the host must pull the 1wire bus low to read a bit. data is guaranteed to be valid within 1 m s of this falling edge and will remain valid for 14 m s minimum. (15 m s total from falling edge on 1wire bus.) 6. v ih is a function of the external pullup resistor and the v cc supply. 7. 30 nanocoulombs per 72 time slots @ 5.0v. 8. at v cc =5.0v with a 5k w pullup to v cc and a maximum time slot of 120 m s. 9. capacitance on the data pin could be 800 pf when power is first applied. if a 5k w resistor is used to pull up the data line to v cc , 5 m s after power has been applied the parasite capacitance will not affect normal communica- tions. 10. maximum 1wire voltage for programming parameters is 11.5v to 12.0v; temperature range is 40 c to +50 c. 11. under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 12. the accumulative duration of the programming pulses for each address must not exceed 5 ms.

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